1. Field of the Invention
The present invention relates to novel designs of a configuration manager for a reconfigurable processor. More particularly, but not by way of limitation, the present invention relates to a configuration manager for a reconfigurable processor having a configuration loader determining whether one or more reconfigurable slots for reconfigurable execution units are available and reconfiguring at least one available reconfigurable slot with a chosen configuration.
2. Background of the Related Art
In contrast to a static processor, the architecture of the hardware and/or the instructions supported by a reconfigurable processor can be changed dynamically. This means that the type and quantity of circuitry implementing particular instructions, or functionality, can be changed after fabrication of the processor and even during execution. A main objective of this work is to increase the achieved instruction level parallelism of the processor by best matching the processor configuration to the instructions that are ready to be executed. The particular focus of the patent is on the design of a configuration manager for a reconfigurable superscalar processor.
There are three main paradigms for the design of reconfigurable processors; these paradigms are based on how the reconfigurable hardware of the processor is interfaced with other components of the architecture [1]. The three paradigms are: (1) attached processor, (2) co-processor, and (3) functional unit. In the attached processor paradigm, the reconfigurable hardware is connected to a host processor via an I/O bus (e.g., a PCI or OPB bus). A host processor controls the operation of the reconfigurable hardware via the bus; and/or data is transmitted between the reconfigurable hardware and the host processor using the bus [1]. An example of a system that uses the attached processor approach is PipeRench [2].
The co-processor paradigm attaches the reconfigurable hardware directly to the host processor in a fashion similar to a floating-point co-processor [1]. One example of this approach is Garp [3].
The final paradigm, the functional unit approach, integrates the reconfigurable hardware into the processor as a functional unit; reconfigurable function units are referred to as RFUs in [1]. OneChip98, SPYDER, and PRISC are examples of the RFU paradigm [1, 4, 5]. The architecture considered in this patent is in the RFU paradigm. One advantage of this paradigm is that it closely models the design of a traditional processor and many existing design concepts can be applied to such a processor.
Examples of previous work in the area of applying reconfigurable architectures to general-purpose computing requirements are SPYDER [4] and PRISC [5]. SPYDER uses a single RFU to implement hardware synthesized specifically for a program to be executed on the processor [4]. A C++ to netlist (a hardware description code) compiler that creates the binary configuration code used to configure the RFUs must be run before a program can be executed on SPYDER [6]. Thus, SPYDER requires that source code must be available and recompiled.
PRISC [5] is a reconfigurable processor similar in concept to SPYDER. A main difference between the two is that the reconfigurable resources in PRISC consist of multiple RFUs connected to the data path of the CPU along with static functional units [5]; SPYDER does not specify static functional units. For programs to utilize the reconfigurable resources of PRISC, they must be analyzed by a hardware extraction tool that determines what program code should be executed using the reconfigurable resources [5].
The SPYDER and PRISC processors represent an important step in applying reconfigurable computing to the realm of general-purpose computing; however, they may lack mainstream viability because they are not legacy-compatible at the level of binary code. Consider the vast amount of legacy software and hardware systems that dominate today's market.
Our motivation is to study general-purpose reconfigurable processors that can execute machine code compiled for current or legacy architectures. Research in this direction has already been undertaken in reference [7], where a general-purpose reconfigurable processor is proposed and modeled. The architecture introduced in reference [7] is based on a set of predefined configurable modules, each of which defines a different configuration of the reconfigurable functional units available in the architecture. These modules can be dynamically loaded at run-time to best match the needs of the instructions currently being executed by the processor. In order for such an approach to work efficiently, the configuration manager portion of the processor must be able to quickly determine the best configuration at any point in time based on the signature of the instructions in the instruction queue or buffer that are ready to be executed.
The work presented in this patent proposes a fast and efficient configuration selection circuit that performs the task assigned to the configuration manager in the architecture proposed in reference [7]. An overview of the architecture defined in reference [7] and the modifications and additions that our work assumes are presented and analyzed in Section 2. One aspect of the approach proposed here is that it uses a set of predefined modules, similar to those proposed in reference [7], and melds them into configurations of the functional units that best match the needs of the system at any given time using partial reconfiguration. The techniques presented in this patent can applied to other architectures in addition to the architecture of reference [7] and its modified version proposed here.